MIPS: Two RISC-V processor cores – design

MIPS, which emerged in 2021 after Wave Computing’s Chapter 11 bankruptcy proceedings, had already announced at the time that it would develop RISC-V processor cores, and now two have been introduced: the eVocore P8700 and the eVocore I8500 IP core.

MIPS is back, the former provider of RISC-IP cores this time does not rely on its own architecture, but on RISC-V. The new processor cores are the first IP cores from MIPS based on RISC-V ISA. With this, the company wants to shift to the road to success and refers to forecasts from Semico Research: According to market analysts, the average annual growth (CAGR) for SoCs delivered with RISC-V cores should be 73.6 percent between 2020 and 2027 The car segment is expected to show a CAGR of 69.9 percent during this period. Rich Wawrzyniak, Principal ASIC and SoC Analyst at Semico Research, believes that RISC-V will increasingly be used in segments such as the automotive industry because this architecture allows companies to differentiate thanks to an open source software development environment. And further: “Given MIPS ‘long tradition as a supplier of RISC architectures and cores and its strong presence in the automotive industry, networks and other high-performance applications, the transition to RISC-V makes sense for the next phase of the company’s growth.”

And Desi Banatao, CEO of MIPS, adds: “With the transition to RISC-V, MIPS is targeting the high-performance segment of the processor market. By leveraging our differentiation in real-time capabilities, hardware virtualization, functional security and security technologies, we can offer compelling products for the automotive industry, edge computing, networking and switching and large-scale computing. “

eVocore IP

With the new scalable and configurable eVocore IP cores, developers can implement cohesive clusters with multi-thread and multi-core CPUs that can be precisely tailored to the requirements of the respective application in terms of power consumption and performance. The IP cores serve as a flexible basis for heterogeneous computing devices because a coherence manager can be used to combine eVocore IP cores and add other accelerator IPs.

Because RISC-V ISA allows the addition of custom features in the form of custom instructions (UDIs), MIPS has implemented proven and powerful features required in many advanced applications, while still keeping the cores fully compatible with standard RISC-V development tools. and software libraries are.

Both eVocore IP cores support hardware virtualization, custom extensions, multi-threading, hybrid debugging, and functional security. Thanks to these features and the high scalability, MIPS believes that the new cores are particularly suitable for computer-heavy tasks in a wide range of markets and applications such as the automotive industry (ADAS, AV, IVI), 5G and wireless networks, data centers and storage and high-performance embedded applications .

The eVocore P8700 core is trimmed for high performance. The multiprocessing system combines a deep pipeline with OOO execution (Out of Order: This allows you to advance instructions if the current instruction is blocked) to achieve high computing power. According to MIPS, this IP kernel is characterized by higher computing power in single-thread applications than all previous RISC-V IP kernels. The cores support scaling up to 64 clusters, 512 cores and 1,024 threads.

The eVocore I8500 core, on the other hand, is trimmed for high efficiency. In this case, MIPS relies on in-order processing to achieve the highest possible current efficiency in SoCs. Each I8500 processor core combines multi-threading and an efficient triple-issue pipeline to achieve very good computing throughput.


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